This application claims the benefit of Korean Patent Application No. 1999-57330 filed on Dec. 13, 1999, under 35 U.S.C. xc2xa7119, the entire contents of which are herein fully incorporated by reference.
1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing the liquid crystal display device (LCD) with a four-masks process.
2. Description of Related Art
An LCD device has a lower substrate or array substrate having switching elements and pixel electrodes, and an upper substrate having a common electrode. Between the lower and upper substrates liquid crystal material is filled.
For more detailed explanation, the array substrate needs more processes than the upper substrate does. The switching element has a gate electrode, a source electrode, a drain electrode, and an active layer. The source electrode is extended from a data line and the gate electrode is extended from a gate line. The gate and data lines cross each other to form a matrix shape, and every region that is defined by crossing the gate and data lines is called a pixel region.
In order to form one layer of the array substrate, a deposition process, a photolithography process, and an etching process are needed. Sometimes, the photolithography process is said to include the deposition process and the etching process. For an array substrate, an insulating material, a semiconductor material, and a conductive material are used.
For the insulating material, a non-transparent material such as silicon nitride and silicon oxide, and a transparent polymer material such as benzocyclobutene (BCB) are used. For the active layer, there are two types: amorphous silicon and poly crystallized silicon. For the conductive material, aluminum, aluminum alloy, molybdenum, tantalum, and molybdenum-tungsten alloy are used.
A chemical vapor deposition method, a sputtering method and other methods are used in order to deposit the materials. For the etching process, a wet etching process and a dry etching process are used. The wet etching process is generally used for etching the conductive material for the gate and data lines and pixel electrode. The dry etching process is generally used for smaller and more accurate pattern such as active layer and insulating layer, and some conductive layers.
Since one mask process requires deposition and lithography and etching processes, it is necessary to reduce the number of masks for manufacturing the array substrate. Thus, recently the four-mask process is suggested. But, in this method, more than one layer should be etched, deteriorating uniformity of the etched layer.
Hereinafter, a manufacturing method for an array substrate is explained with reference to drawings.
FIG. 1 is a partial plane view of a typical array substrate for an LCD device. There is shown a thin film transistor xe2x80x9cTxe2x80x9d near the cross point of the data and gate lines 13 and 15, which also define the pixel region xe2x80x9cPxe2x80x9d. There is also shown a storage capacitor xe2x80x9cCstxe2x80x9d that must have a first electrode and a second electrode. The gate line 15 acts as the first electrode for the capacitor xe2x80x9cCxe2x80x9d and the pixel electrode 17 acts as the second electrode for the capacitor xe2x80x9cCstxe2x80x9d.
The storage capacitor xe2x80x9cCstxe2x80x9d helps to maintain the transmitted signal to the liquid crystal material during between the transmitting signals. The storage capacitor is electrically parallel to the liquid crystal material. The storage capacitor can be formed as shown in FIG. 1 or independent of the gate line 15. The former is called storage capacitor-on-gate (Cst-on-Gate) structure, and the latter is called independent storage capacitor structure. These days the former structure shown in FIG. 1 is generally adopted.
FIGS. 2A to 2D are cross sectional views taken along line IIxe2x80x94II of FIG. 1. These drawings illustrate a manufacturing process of the array substrate according to a related art.
As shown in FIG. 2A, in order to form a gate line 15, first a conductive material is deposited on the substrate 11 to form a first metal layer. The conductive material is chosen from a group consisting of aluminum, molybdenum, tungsten, and so on. Sometimes dual layer structure of aluminum and chrome or tungsten is adopted. On the entire first metal layer, a photoresist is coated. Then using a first mask having a gate line shape, the photoresist is exposed to light, and some of the photoresist is removed, leaving a portion of photoresist having a gate line pattern. Then, the first metal layer is etched to form a gate line and the remaining photoresist is removed.
FIG. 2B illustrates a second mask process. On the gate line 15 and the substrate, a gate insulating layer 19 made of a gate insulating layer, a semiconductor layer 21 made of a pure amorphous silicon layer, an ohmic contact layer, and a conductive material layer or second metal layer are formed and stacked sequentially. Then using a second mask, after the lithography process explained above with reference to FIG. 2A, the second metal layer is etched to form a data line 13 crossing the gate line 15 and a metal portion 13a having an island shape above the gate line 15. After that, the ohmic contact layer is etched to form an ohmic contact layer 22 having the same pattern as the data line 13 and the metal portion 13a. 
FIG. 2C illustrates a third mask process. An insulating material is deposited on the whole substrate after the process shown in FIG. 2B to form a protection layer 23. Then using a third mask, photoresist 27 is only left over the data line 13 and over a portion for a thin film transistor xe2x80x9cTxe2x80x9d (see FIG. 1). Thus, portions of the array substrate can be divided into three portions: xe2x80x9cAxe2x80x9d portion having the photoresist 27 and other layers; xe2x80x9cBxe2x80x9d portion having a sectional structure composed of the gate insulating layer 19, semiconductor layer 21 and protection layer 23; and xe2x80x9cCxe2x80x9d portion having a sectional structure composed of the gate line 15, gate insulating layer 19, semiconductor layer 21, ohmic contact layer 22, metal portion 13a and protection layer 23. As can be imagined from FIG. 1, xe2x80x9cAxe2x80x9d portion corresponds to a data line portion, xe2x80x9cBxe2x80x9d portion to a pixel region xe2x80x9cPxe2x80x9d, and xe2x80x9cCxe2x80x9d portion to a storage capacitor portion xe2x80x9cCstxe2x80x9d.
As shown in FIG. 2D, using the photoresist 27, xe2x80x9cAxe2x80x9d, xe2x80x9cBxe2x80x9d, and xe2x80x9cCxe2x80x9d portions are all etched at the same time with only a single etching gas using a dry etching method. As a result, at xe2x80x9cAxe2x80x9d portion, the layers 23, 22, 21, 13, and 19 under the photoresist 27 are left; at xe2x80x9cBxe2x80x9d portion, no layer is left; and at xe2x80x9cCxe2x80x9d portion, the gate insulating layer 19a having a non-uniform thickness xe2x80x9ctxe2x80x9d is left due to the etching rate and metal portion 13a shown in FIG. 2C. The gate insulating layer 19a on the gate line 15 acts as a dielectric layer of the storage capacitor xe2x80x9cCxe2x80x9d (see FIG. 1).
However, since multiple layers are simultaneously etched at one time using a single etching gas and the gate insulating layer should remain on the gate line 15, the remaining gate insulating layer 19a cannot have a uniform thickness throughout the whole pixel regions xe2x80x9cPxe2x80x9d (see FIG. 1) and/or their boundaries and cannot have a smooth surface as shown in FIG. 2D. Thus the capacitance of the capacitor xe2x80x9cCstxe2x80x9d varies according to the position of the pixel region and the property of the capacitor is degraded due to a surface roughness of the gate insulating layer 19a, which results in deteriorating display quality of the LCD device.
To overcome the problems described above, preferred embodiments of the present invention provide a method of manufacturing an array substrate for use in a liquid crystal display device which can make storage capacitor on the gate line have a uniform capacitance independent of the position of the pixel region.
Preferred embodiments of the present invention further provide another method of manufacturing an array substrate for use in a liquid crystal display device having a short processing time and a high manufacturing yield.
In order to achieve the above objects, the preferred embodiment of the present invention provides a method of manufacturing an array substrate for use in a liquid crystal display device, including: providing a substrate; forming a gate line on the substrate using a first mask; forming sequentially a gate insulating layer, a semiconductor layer, a doped semiconductor layer, and a metal layer on the the whole substrate while covering the gate line; forming a data line and an island shaped metal portion with the doped semiconductor layer on the semiconductor layer over the gate line by patterning the metal layer using a second mask; forming a protection layer on the semiconductor layer while covering the data line and the island shaped metal portion; forming a photoresist pattern on the protection layer over the data line using a third mask to define a first interstructure; etching the first interstructure using the photoresist pattern to leave the photoresist and the layers under the the photoresist over the data line and to leave the etched semiconductor layer and the gate insulating layer over the gate line to define a second interstructure; etching the second interstructure to leave the gate insulating layer on the gate line; and forming a pixel electrode covering a portion of the gate insulating layer on the gate line using a fourth mask.
In an another aspect of the invention, the preferred embodiment of the present invention further provides a method of manufacturing an array panel for use in a liquid crystal display device, including: providing a substrate; forming a gate line on the substrate using a first mask; forming sequentially a gate insulating layer, a semiconductor layer, a doped semiconductor layer, and a metal layer on the whole substrate while covering the gate line; forming a data line and an island shaped metal portion with the doped semiconductor layer on the semiconductor layer over the gate line by patterning the metal layer using a second mask; forming a protection layer on the semiconductor layer while covering the data line and the island shaped metal portion; forming a photoresist pattern on the protection layer over the data line using a third mask to define a first interstructure; etching the first interstructure using the photoresist pattern to leave the photoresist, the layers under the photoresist over the data line and to leave the island shaped metal portion, the doped semiconductor layer, the semiconductor layer, and the gate insulating layer over the gate line to define a second interstructure; etching the second interstructure to leave the semiconductor layer and the gate insulating layer on the gate line to define a third interstructure; etching the third interstructure to remove the semiconductor layer and the gate insulating layer on the gate line; and forming a pixel electrode covering a portion of the gate insulating layer on the gate line using a fourth mask.